Sr Advanced ASIC FPGA Verification Engineer

Responsibilities for this Position

Sr Advanced ASIC FPGA Verification Engineer

ID: 2026-70286
USA-AZ-Scottsdale
Required Clearance: TS/SCI, obtainable within reasonable time based on requirements
Posted Date: 1/20/2026
Category: Engineering-Hardware
Employment Type: Full Time
Hiring Company: General Dynamics Mission Systems, Inc.

Basic Qualifications

Requires a Bachelors degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 8+ years of job-related experience, or a Master's degree plus 6 years of job-related experience. Agile experience preferred.

Clearance Requirements:

Department of DefenseTS/SCI security clearance ispreferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

Primary Job Qualifications:

We encourage you to apply if you have any of these preferred skills or experiences:

• In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
• In-depth knowledge of System Verilog object oriented programming and the Universal Verification Methodology (UVM)
  • Understands UVM Testbench Architectures
  • Comfortable using and developing UVM agents , bus functional models
  • Understands different types of coverage , usage of cover classes, cover points, etc
  • Experience with predictive testbench components, functional coverage and assertions
  • Experience with constrained random testing
  • Experience with the Register Abstraction Layer
• Familiarity with requirements-based verification , requirement tracing, and developing requirement verification strategies etc
• Experience with scripting languages such as Linus shell scripts, TCL, Python
• Familiarity with using Formal Verification tools, code coverage, writing waivers etc
• Familiarity with the following are also helpful
  • Questa Verification IP ( QVIP )
  • Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs
  • AXI protocols, PCIe, Space Wire, and Ethernet interfaces
  • DSP functions and common signal processing components
  • Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
  • Continuous Integration features of GITLab

Duties and Tasks:
Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
Determines architecture, system simulation and detailed design approach
Defines module interfaces and all aspects of device design and simulation
Creates test and simulation plans that establish functional criteria
Verifies test results and analyzes performance
May also review vendor capabilities and simulation tools
Participates in the improvement of the ASIC/FPGA organizational processes
Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
May provide leadership and/or direction to lower level employees
Independently determines approach to solutions
Contributes to the completion of major programs and projects
Plans and executes project tasks for activities described above

General Knowledge, Skills and Abilities:
This candidate must have an ability to operate in a team environment and learn new skills to accomplish the verification goals.
Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
Proficient in the principles and techniques of ASIC/FPGA design and the design process
Keeps abreast of technology trends
Proficient awareness of business objectives and Engineerings role in achieving
Proficient in Microsoft Office applications
Proficient written and verbal communications skills
Ability to think creatively
Ability to multi-task
Proficient skill in communicating issues, impacts, and corrective actions
Regular contact with senior levels of internal work groups
Works under limited direction
Contact with project leaders and other professionals within the Engineering department and with project teams across the company
Some contact with external customers

Workplace Options:
This position is fully on-site or hybrid/flex, as mutually agreed.
While on-site, you will be a part of theScottsdale, AZ team. Learn more at

Key Words : Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing

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#CJ1

Salary Note

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range

USD $152,462.00 - USD $169,138.00 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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