Senior ASIC Verification Engineer
- Strong understanding of Object Oriented Programming (classes, methods, polymorphism)
- Use of a high-level language for verification, such as SystemVerilog C++, Java, etc.
- Experience with verification methodologies (OVM/UVM)
- Highly skilled with one or more industry standard simulation tools such as Mentor Questa-ModelSim, Synopsys
VCS, or Cadence NCSIM
- Strong understanding of typical design structures (FIFO’s, pipelines, memories, state machines, etc.)
- Strong understanding of standard protocols (PCI Express, Ethernet, etc.)
- Comfortable and confident interacting with customers
- Excellent written and verbal communication skills
The following additional skills and experiences would be a plus:
- Experience verifying hierarchically partitioned large ASICs
- SystemVerilog/C++ co-simulation
- Overall knowledge of the ASIC development process
- RTL design experience
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