Analog Models & Verification Engineer, Architect - 13485

On-site work is being considered for either Chandler, AZ, Markham or Mississauga, Canada.
We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

An accomplished verification engineer with deep expertise in mixed-signal systems, passionate about real number modeling (RNM) you will translate the nuanced behavior of leading-edge analog circuits into high-fidelity, scalable behavioral models. You’ll collaborate across engineering disciplines, driving model creation, integration, and continuous improvement for world-class SerDes verification. Your work will directly enhance the performance, efficiency, and quality of Synopsys' 224G & 448G connectivity products.

What You’ll Be Doing:

• Work closely with analog circuit teams to extract all necessary details, simulate, and sign off on high-fidelity models by rigorous comparison with SPICE-level simulations and silicon data
• Develop and refine behavioural models of the analog portions of high-speed SerDes blocks (TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator).
• Ensure models accurately capture all relevant functionalities, calibration/adaptation controls, time- and mode-dependent behaviors, key performance aspects, and residual impairments (offsets, gain mismatches, jitter, noise, skew, supply noise, etc.).
• Interface with digital design and verification teams to guarantee exhaustive model verification—ensuring all functionalities and edge-cases are included in regression and integration test plans.
• Reviewing execution against verification plans through regular meetings with multiple verification teams (analog, cosim, DV, GLS, formal, emulation).
• Integrate behavioral models into modern verification environments (UVM, MS-MDV), utilizing assertion-based checks, analog/digital interface scoreboards, and power-aware techniques as appropriate.
• Optimize model implementations for simulation speed and accuracy.
• Drive continuous improvement and automation in the creation, maintenance, and validation of SerDes behavioral models.
• Establish and evangelize best practices and reusable frameworks for efficient, scalable RNM modeling and mixed-signal verification.
• Mentor and support teammates, sharing knowledge, methodology innovations, and documentation.

The Impact You Will Have:

• Enable rapid, rigorous, and coverage-driven verification of SerDes IP by deploying and validating high-quality RNM models.
• Dramatically accelerate verification workflows—reducing dependence on AMS simulations and delivering faster, more predictable project schedules.
• Deliver signoff-quality RNM models, validated against both SPICE simulation and silicon, to empower high-confidence tapeouts and market-leading silicon.
• Solidify Synopsys’ reputation for high-performance, reliable, and thoroughly verified mixed-signal connectivity IP.
• Enable successful silicon implementation by catching issues early through rigorous simulation and verification.
• Facilitate cross-team collaboration that enhances product quality and reliability.

What You’ll Need:

• BSc, MSc or PhD in Electrical/Computer Engineering, with 7+ years of relevant industry experience.
• Advanced proficiency with Verilog, SystemVerilog (including RNM, wreal modeling, and IEEE 1800-2012 SV-DC extensions).
• Robust understanding of analog/mixed-signal SerDes sub-blocks: TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator.
• Proven ability to model analog circuit impairments: offsets, gain/mismatches, jitter, noise, skew, supply noise, etc.
• Fluency with analog schematics, SPICE-level simulation tools and waveform analysis.
• Strong scripting/programming in Python, TCL, Perl, C/C++.
• Familiarity with verification flows: regression, analog/mixed-signal co-simulation, digital verification, gate-level simulation, formal methods, and emulation.
• Experience with UVM testbenches, assertion-driven and coverage-driven verification.

Who You Are:

• Comfortable with engaging across analog, digital, and mixed-signal teams.
• Self-starter who welcomes challenges and proactively identifies and solves problems.
• Constantly seeking ways to improve workflows, methodologies, and modeling quality.
• Detail-focused and thoughtful—always considering boundary/edge-cases and full use-case coverage.
• Strong communicator and mentor, able to share knowledge and guide others.
• Adaptable, thriving in fast-paced and evolving environments.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.